The present invention relates to a semiconductor integrated circuit device for communication, which is equipped with a PLL (Phase Locked Loop) circuit, and particularly to a technique beneficial to a fractional PLL circuit or fractional synthesizer including a fraction (decimal fraction) as well as an integer as a division ratio.
In a general PLL circuit whose division ratio is an integer alone, the frequency resolution of a locked loop becomes a reference frequency fREF. Therefore, the accurate frequency resolution needs a small reference frequency fREF. Thus, it becomes a small loop frequency band. It is not desirable to use a narrow loop frequency band because it becomes a long switching time. The suppression of phase noise of a voltage-controlled oscillator (VCO) in the PLL circuit is insufficient and the PLL circuit is hence susceptible to noise produced from outside the PLL circuit.
According to a non-patent document 1 (Brian Miller and Robert J. Conley “A Multiple Modulator Fractional Divider”, IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 40. NO. 3. JUNE 1991, PP. 578-583), a fractional synthesizer is developed to have frequency resolution more accurate than a reference frequency fREF. In a fractional N divider, its division ratio is periodically changed from N to N+1. Eventually, a means or average division ratio is increased by a duty ratio of (N+1) division than N. An overflow from an accumulator is used to modulate an instantaneous division ratio.
Thus, in the fractional PLL circuit, the division ratio N of a divider in a negative feedback loop thereof is a rational number including a fraction (decimal fraction) as well as an integer. It has been described in a non-patent document 2 (Tom A. D. Riley et al “Delta-Sigma Modulation in Fractional-N Frequency Synthesis”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28. NO. 5. MAY 1993. PP. 553-559) that a wide loop band relative to given channel spacing enables high-speed/settling time by the fractional N division and a phase noise request required of a voltage-controlled oscillator is also reduced or decreased. The non-patent document 1 also describes a dual modulus divider in which a division ratio related to an accumulator of a primary or first-order ΔΣ modulator (also called “ΣΔ modulator”) is n/n+1. The condition for the overflow of the accumulator is used in shift for division to n+1. Further, it has been reported in the non-patent document 2 that a spurious output frequency at a fractional frequency synthesis is also reduced by a high-order noise shaving technique based on high-order ΔΣ modulation for the fractional N division.
Further, a fractional N frequency synthesizer using MASH (Multistage noise Shaping Technique) in which a plurality of primary or first-order ΣΔ modulators are configured in multistage form, has been reported in a non-patent document 3 (A. E. Hussein and M. I. Elmasry “A FRACTIONAL-N FREQUENCY SYNTHESIZER FOR WIRELESS COMMUNICATIONS”, 2002 IEEE International Symposium Circuits and Systems, PP. IV-513-IV-516).